Volume 12 Issue 2 - January 1, 2010 PDF
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On-Resistance Degradation Induced by Hot-Carrier Injection in LDMOS Transistors with STI in the Drift Region
Jone F. Chen*, Kuen-Shiuan Tian, and Shiang-Yu Chen
Institute of Microelectronics, Department of Electrical Engineering
 
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High-voltage devices are integrated into CMOS technologies to fulfill the trend of lower cost and smaller chip size in recent specific high-voltage products. Lateral DMOS (LDMOS) transistors are the suitable devices to be integrated into smart-power applications because of their compatibility with CMOS process. Because LDMOS devices are usually operated under high drain voltage (Vds) and high gate voltage (Vgs), hot-carrier-induced degradation is a major reliability concern in LDMOS transistors. In this work, the phenomenon and mechanisms of hot-carrier-induced on-resistance (Ron) degradation in n-type LDMOS transistors with shallow trench isolation (STI) in drift region are investigated. Based on experimental data and technology computer-aided-design (TCAD) simulation results, the mechanisms responsible for Ron shift are discussed.

Fig. 1. Schematic cross section of the n-type LDMOS device used in this work.
Fig. 1 shows the schematic cross section of the n-type LDMOS transistor used in this work. This device is integrated into a 0.25-μm CMOS process and features a STI in n- drift region near the drain. The channel length is about 0.3 μm. The gate oxide thickness and gate width of the device are 30 nm and 10 μm, respectively. The operational voltages are Vds = 40 V and Vgs = 12 V. To investigate hot-carrier-induced degradation, stressing under Vds = 40 V and various Vgs is performed at room temperature with source and substrate connected to the ground. The stress tests are interrupted periodically to measure the degradation of device parameters including Ron. Ron (= Vds/Id, where Id is drain current) is measured under Vds = 0.1 V and Vgs = 12 V. Two-dimensional TCAD simulations are also performed to explain the experimental results.

Fig. 2. Ron shift as a function of stress time for the device stressed under Vds = 40 V and Vgs = 12 V.
Two substrate current (Isub) peaks are observed in Isub-Vgs characteristics in our LDMOS devices. The first Isub peak occurs at Vgs = 4 V that is similar to the behavior in conventional MOSFETs. As Vgs > 8 V, Isub rises again because of Kirk effect and the second Isub peak occurs at Vgs = 12 V. When our LDMOS devices are stressed under Vds = 40 V with various Vgs (2.5, 4, 8, and 12 V), the device stressed under Vgs = 12 V degrades the most. As a result, the following analysis is focused on the device stressed under Vgs = 12 V. Fig. 2 shows Ron shift as a function of stress time for the device stressed under Vds = 40 V and Vgs = 12 V. An unexpected reduction in Ron is observed at the beginning of stress. When the stress time is shorter than 10 s, Ron is smaller than its fresh value (Id increases). As the stress time is longer than 10 s, Ron is greater than its fresh value (Id decreases).

To investigate the mechanism of Ron degradation, TCAD simulation results are analyzed. Fig. 3(a) shows simulated impact ionization (ii) rate along Si/SiO2 interface when the device is biased at Vds = 40 V and Vgs = 12 V. Results show that an ii peak exists at the STI corner closest to the channel. Another severe ii generation caused by Kirk effect occurs at the STI edge closest to the drain. Fig. 3(b) shows simulated vertical electric field (Ey) along the Si/SiO2 interface under the same bias condition. Positive Ey indicates that the direction of Ey is pointing downward and is favorable for electron injection. Negative Ey, on the contrary, is favorable for hole injection. From Fig. 3(a) and Fig. 3(b), the mechanisms of Ron degradation are suggested as follows. At the STI corner closest to the channel, energetic electron-hole pairs are generated because of severe ii generation. Holes are injected into STI because of negative Ey. Such a hot-hole injection may create hole trapping. Trapping of holes in STI induces negative mirror charges at Si/SiO2 interface in drift region, resulting in an effective increase in drift region concentration. As a result, Id increases and Ron decreases. This inference explains why Ron is reduced at the beginning of stress. On the other hand, the severe ii generation at the STI edge closest to the drain results in hot-electron injection because of positive Ey. Such an electron injection may create electron trapping and interface trap (Nit), leading to Ron increase. The damage created at the STI edge closest to the drain is expected to dominate Ron degradation as the stress time is longer. This explains why Ron is greater than its fresh value after 10 s as in Fig. 2.
Fig. 3. Simulated (a) ii rate, (b) vertical electric field along the Si/SiO2 interface under Vds = 40 V and Vgs = 12 V.

To verify the existence of hole trapping, Fig. 4 shows Id shift measured at different Vgs as a function of stress time for the device in Fig. 2. When Id is measured at low Vgs (= 3.5 V), the current path under STI is deeper. This argument can be confirmed in Fig. 5, where the simulated accumulated current as a function of the depth from Si/SiO2 interface at the location of the STI corner closest to the channel is shown. The current is accumulated from the bottom of n- region to Si/SiO2 interface. Results show that the accumulated current near Si/SiO2 interface under Vgs = 3.5 V rises less rapidly than that under Vgs = 12 V, indicating that current path is away from Si/SiO2 interface at low Vgs. As current flows deeper, the effect of negative mirror charges on Id increase is less apparent. Thus, Id decreases monotonously during stress when Id is measured at Vgs = 3.5 V as in Fig. 4. The results in Fig. 4 reveal that hole trapping is responsible for the unexpected Ron reduction in the early stage of stress.
Fig. 5. Simulated accumulated current as a function of the depth from Si/SiO2 interface at the location of bottom-left corner of STI.
Fig. 4. Id shift measured at different Vgs as a function of stress time for the device in Fig. 2.

In conclusion, the phenomenon and mechanisms of hot-carrier-induced Ron degradation in n-type LDMOS transistors with STI in drift region are discussed. Ron decreases at the beginning of stress but Ron increases afterwards. Experimental data and TCAD simulation results suggest that Ron reduction is attributed to hot-hole injection and trapping at the STI corner closest to the channel. According to results presented in this study, the unexpected Ron decrease should be paid special attention in evaluating LDMOS transistors’ reliability.
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