Volume 8 Issue 3 - April 3, 2009
Effect of hot-carrier-induced interface states distribution on linear drain current degradation in 0.35 um n-type lateral diffused metal-oxide-semiconductor transistors
Jone F. Chen* and J. R. Lee

Institute of Microelectronics, College of Electrical Engineering and Computer Science, National Cheng Kung University
jfchen@mail.ncku.edu.tw

Applied Physics Letters, Vol. 92, pp. 103510, March 2008

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High-voltage lateral diffused MOS (LDMOS) transistors are widely used in smart power applications because they are easily to be integrated into standard CMOS process. Because of relatively high operational voltages, LDMOS transistors are prone to hot-carrier-induced degradation. The investigation of the mechanism of hot-carrier-induced linear drain current (Idlin) degradation (increase of on-resistance) is necessary because transistors with a lower on-resistance produce smaller power consumption. To evaluate this concern, this work presents the mechanisms of hot-carrier-induced Idlin degradation in n-type LDMOS devices.

Devices investigated in this study are n-type LDMOS transistors fabricated by a 0.35 μm CMOS process. Figure 1(a) shows schematic cross-section of the device. The p-type channel region (Lch), n-type accumulation region under poly-gate (Lacc), and drain side spacer region (Lsp) are indicated in the figure. Gate oxide thickness of the device is 30 nm and poly-gate length is 0.8μm. Operational voltage for both drain voltage (Vds) and gate voltage (Vgs) is 12 V. To evaluate the damage created by hot carriers, stressing under Vds = 13.2 V and various Vgs ranging from 3 to 11 V for 3000 seconds is performed at room temperature. Idlin is measured under Vds = 0.1 V and Vgs = 12 V. Threshold voltage (Vth) is extracted under Vds = 0.1 V using maximum transconductance method. During stressing, Idlin, Vth, and charge pumping current (ICP) are monitored periodically. ICP is measured to extract stress-induced interface state density (ΔNit). Figure 1(b) shows the experimental setup of charge pumping measurement performed in this work. The pulse in charge pumping measurement is applied to the gate while drain and bulk terminals are grounded. The source terminal is floating. The amplitude of the pulse is fixed at 10 V and base voltage (Vbase) sweeps from -8 to 2 V under a frequency of 500 kHz. Process (TSUPREM4) and device (Medici) simulations are also performed to investigate the mechanism of hot-carrier-induced degradation.
Fig. 1. (a) Schematic cross-section of the n-type LDMOS device used in this work. (b) The experimental setup of charge pumping measurement.

Figure 2(a) shows Idlin degradation and Vth shift as a function of stress time for devices stressed under Vds = 13.2 V and Vgs ranging from 3 to 11 V. Results show that higher Vgs produces more Idlin degradation. For devices stressed under Vgs = 3 to 9 V, Vth shift is little (< 5 mV), indicating that hot-carrier-induced damage located in Lch region is small. Most of the damage is located in Lacc and Lsp regions. However, Vth shift is more than 10 mV when the device is stressed under Vgs = 11 V, revealing that damage location moves into Lch region. Bulk current (Ib) vs. Vgs characteristics under various Vds is shown in Fig. 2(b). It is clear that Kirk effect is not significant in our LDMOS device because Ib does not increase at high Vgs (Vgs = 12 V). Thus, the impact of Kirk effect on device degradation is not taken into consideration in the following analysis.
Fig. 2. (a) Idlin degradation and Vth shift as a function of stress time for devices stressed under Vds = 13.2 V and Vgs ranging from 3 to 11 V. (b) Ib vs. Vgs characteristics under various Vds.

To investigate the degradation mechanism, Fig. 3 analyzes stress-induced increase in ICP (ΔICP) for the devices shown in Fig. 2(a) stressed for 3000 seconds. The location dependent Vth and flat band voltage (Vfb) obtained from TCAD simulations are investigated and the results are shown in Fig. 4. Based on Vth and Vfb distributions obtained in Fig. 4, ΔICP measured at Vbase = -8 V is proportional to total ΔNit, i.e., ΔNit in Lch, Lacc, and Lsp regions. Similarly, ΔICP measured at Vbase = -2 V is proportional to ΔNit located in Lch and Lacc regions, while ΔICP measured at Vbase = 0.5 V is proportional to ΔNit located in Lch region only. According to the above analysis, little ΔICP is observed at Vbase = 0.5 V for devices stressed under Vgs = 3 to 9 V, indicating that hot-carrier-induced ΔNit is mainly distributed in Lacc and Lsp regions. As the stress Vgs is increased to 11 V, significant ΔICP is observed at Vbase = 0.5 V, suggesting that significant ΔNit is created in Lch region.
Fig. 3. Stress-induced ΔICP as a function of Vbase for the devices shown in Fig. 2(a) stressed for 3000 seconds.
Fig. 4. Location dependent Vth and Vfb as well as Idlin degradation resulted from ΔNit at different locations are simulated.

Since ΔNit is located at various regions, the impact of damage location on Idlin degradation should be examined. This can be achieved by TCAD simulations. The same amount of interface states distributed in a range of 0.05 μm but centered in different locations are assigned from channel to spacer edge in simulations. Idlin degradation resulted from interface states at different locations are shown in Fig. 4. Results reveal that interface states in Lsp region produce the most Idlin degradation. Interface states in Lch region also degrade Idlin but not as much as that of damage in Lsp region. Interface states in Lacc region produce the least Idlin degradation. To confirm the above argument, Fig. 5 shows the relationship between device Idlin degradation and the average interface states density in spacer region (ΔNit_sp). For devices stressed under Vgs = 3 to 9 V, a unified relationship between Idlin degradation and ΔNit_sp is obtained. For the device stressed at Vgs = 11 V, larger Idlin degradation is observed because ΔNit in Lch region also contributes to Idlin degradation. Results in Fig. 5 confirm that when ΔNit in Lch region is negligible, ΔNit in Lacc region is not an important factor and only ΔNit in Lsp region dominates the Idlin degradation.
Fig. 5. Relationship between Idlin degradation and average ΔNit in Lsp region is shown.

In conclusion, mechanisms of hot-carrier-induced Idlin degradation in our n-type LDMOS transistor have been presented. The device degradation is mainly caused by hot-carrier-induced ΔNit. Experimental data and TCAD simulations reveal that ΔNit located in Lacc region has little effect on Idlin degradation, while ΔNit located in Lsp region has great impact on Idlin degradation. According to the results presented in this study, not only the magnitude of total hot-carrier-induced ΔNit but also the location of ΔNit should be considered in evaluating LDMOS transistors’ reliability.
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