Volume 7 Issue 8 - February 27, 2009
A 60-GHz Millimeter-Wave Bandpass Filter Using 0.18-μm CMOS Technology
Cheng-Ying Hsu, Huey-Ru Chuang*

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2007 EE Top 5% ranking paper.


There exists an increasing demand for broadband multimedia applications for an ever increasing capacity of wireless networks.  With its attenuation characteristic of atmospheric oxygen of 10 to 15 dB/km in a bandwidth of about 7 GHz centered around 60 GHz, it makes the 60 GHz band of utmost interest for all kinds of short-range wireless communications. In particular, this unlicensed band can find applications in dense local communications, such as point-to-point wireless LANs and broadband internet access.

To pursue the RF system-on-chip (RF-SoC) for the 60-GHz radio with low-cost monolithically integrated CMOS RF front-end circuitry, a millimeter-wave CMOS RFIC-on-chip passive filter is studied for this aspect [1]. The RF bandpass filter can enhance the performance of a RF front-end in modern wireless communication systems. How to design a bandpass filter with easy integration and good performance is currently of great interest. With the considerations of size miniaturization and RF-SoC integration, the commercial silicon CMOS process will be very effective for high frequency circuit integration. The millimeter-wave CMOS-based bandpass filters with low insertion-loss were earlier developed. However, inadequate selectivity is achieved and the bandwidth is too wide to apply in the 60-GHz Wireless personal area network (WPAN) system which has a bandwidth of about 7 GHz. In [4], a 77 GHz lumped element bandpass filter was fabricated in an advanced SiGe technology. It has some advantages such as small chip area and high selectivity response, however, the insertion loss in its passband is about 7 dB. It has been proven that the dual-mode ring resonator has the characteristics of high selectivity and high Q value [5], [6]. The implementation of a 60-GHz RFIC-on-chip bandpass filter with a 0.18-um CMOS standard is presented. To avoid an additional loss from mismatch, step impedance matching network is considered between metal pad and feeding port. Moreover, the construction of a perturbation stub is employed for increasing the selectivity of the designed filter.
Fig.1. Structure of levels of metal in CMOS process and layout of a 60-GHz CMOS millimeter-wave square loop dual-mode banspass filter


Transmission loss becomes more important as the operating frequency increases. In a CMOS device, currents flowing through capacitive coupling into the silicon substrate can cause an additional loss. To prevent currents from injecting into the substrate and hence reduce the transmission loss, a ground plane is placed above the Si-substrate.  However, the close proximity of the ground plane to the signal line yields the large-distributed capacitance and the small-distributed inductance and hence results in the dropping of self-resonant frequency. A challenge is taking place in providing resonance at frequency of 60 GHz.  A way to overcome this problem is to place the ground plane far away from the filter structure; in this case, the ground plane is placed at bottom metal (M1). For measurement consideration, the probe laid on top level of metal shown in Fig. 1 can be configured with probes and connected to ground plane using via holes. The chip layout of a CMOS dual-mode bandpass filter with enhanced coupling is shown in Fig.1. The related 3-D on wafer measurement setup is shown in Fig. 2. The input and output ports are connected to the square ring resonator through coupling arms at 180˚ and 270˚ and a perturbation stub is positioned at 45˚. With orthogonal feed lines used, two transmission zeros can be excited. Such structure can provide a quasi-elliptic function and reject adjacent channel interferences. The circumference lr of the ring resonator is given by equation (1), where n is the mode number and λg is the guided wavelength.

In this case, λg is about 2.67 mm based on relative permittivity of 3.8 at 64 GHz operating frequency. The splitting of the resonant frequency between two degenerate modes can be caused by increasing the size of the perturbation stub. To obtain better matching between measurement pad and line-to-ring coupling structure, the realization of the input impedance Zin looking into line-to-ring coupling structure needs to be visualized. The input impedance with a value of about 21-70j (Ω) can be estimated. Upward impedance matching network shown in Fig.3, which inductive reactance is in series and capacitive reactance is in parallel, is used to pull the impedance from 21-70j (Ω) to 50 (Ω). Based on transmission line theory, the equivalent circuit for a small θ and large characteristic impedance transmission line is equal to an inductor, while the equivalent circuit for a small θ and small characteristic impedance transmission line is equal to a capacitor. Therefore, two section transmission lines with electrical line lengths of θ1 (=π/3) and θ2 (=π/9) can be modeled as matching network and be easily integrated with ring resonator.


The proposed filter implemented on a 0.18-um CMOS multi-layered structure increases the simulation complexity. A way to reduce this complexity is to evaluate effective dielectric constant and simplify it into a single equivalent homogeneous substrate. Based on the developed formulation [8], the equivalent dielectric constant can be calculated by using

where tn> is the height of the nth substrate layer andεn is the permittivity of the nth substrate layer. The height of the equivalent substrate is taken to equal the total height of the substrates and is given by

Fig 4 shows the chip micrograph of the implemented CMOS filter. the chip size is 1.148 x 1.49 mm2 on a substrate of about 500 μm thickness. The dimensions of the filter are l = 703μm, m = 6μm, w = 2μm, s = 1.5μm and the width of perturbed square stub is p = 75μm. The simulated and measured results are shown in Fig. 5. The 3-dB bandwidth is about 12 GHz at the center frequency of 64 GHz. The insertion loss of the passband is about 4.9 dB and the return loss is better than 10 dB within passband. Most loss is dominated by the conductor loss and the dielectric loss. The out-band rejections are greater than 30 dB within 2-45 GHz and 85-110 GHz.
Fig.2. On wafer measurement setup and probe pad structure
Fig.3  Equivalent circuit of the measurement pad
Fig.4. Chip micrograph
Fig.5. Simulation and measurement results of a 60-GHz CMOS filter.


A typical planar ring resonator structure with dual transmission zeros was employed to design this CMOS filter. The 3-D full-wave EM solver, IE3D, is used for design simulation. Dummy metals and via parasitic effects are considered in the design. The size of the perturbation stub, which can provide a better performance in the stopbands of the filter, is simulated and discussed. The simulated and measured results are in good agreement.This is to pursue the RF System-on-chip (SoC) and single-chip transceiver for a 60-GHz radio.


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