Volume 6 Issue 4 - October 31, 2008
A 60-GHz Millimeter-Wave CPW-Fed Yagi–Antenna Fabricated Using 0.18-μm CMOS Technology
Shun-Sheng Hsu, Kuo-Chih Wei, Cheng-Ying Hsu, and Huey-Ru Chuang*

Institute of Computer & Communication, College of Electrical Engineering and Computer Science, National Cheng Kung University

IEEE Electron Device Letters, vol. 29, no. 6, pp. 625 – 627, June 2008.

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Recently, there exists an increasing demand for broadband multimedia applications for an ever-increasing capacity of wireless networks.  In particular, for dense local communications, the 60- GHz band for wireless personal area network (WPAN) applications is of special interest to the short range communications due to its attenuation characteristic of atmospheric oxygen of 10 to 15 dB/km in a band-width of about 8 GHz centered around 60 GHz. It makes the 60-GHz band becomes an attractive alternative for the short-range wireless communications [1].  In order to pursue the RF system-on-chip (SoC) for the 60-GHz radio and the antenna integrated with low-cost monolithically integrated CMOS RF front-end circuitry, millimeter-wave CMOS RFICs and on-chip antenna have been studied [2]-[4]. In 2006, Zhang et al. have proposed an on-chip inverted-F antenna fabricated on a low-resistivity silicon substrate [5]. In this paper, a 60-GHz CMOS on-chip CPW-fed Yagi antenna is presented. The on-chip antenna is fabricated with a 0.18-μm CMOS process. Various designs of the planar PCB CPW-fed quasi-Yagi antenna has been reported the X-band which use a ground plane acting as a reflector [6], [7].  In our design, the 0.18 μm 6-metal-layer CMOS process (see Fig. 1) allows the on-chip antenna to utilize a simple CPW to CPS feed transition [8] and the first metal-layer to implement a reflector strip. This on-chip antenna design alleviates the  complicated  feeding  network commonly required for the design of quasi-Yagi antenna. The HFSS FEM-based 3-D full-wave EM solver is used for the design simulation. The on-wafer measurement in a microwave probe station is conducted to measure the input SWR and the antenna power gain of the designed on-chip antenna.          
Fig.2  Illustration of HFSS port excitation of the on-chip antenna.
Fig.1  Schematics and cross-sectional view of the designed 60-GHz CPW-fed Yagi CMOS on-chip antenna.


Fig.3  (a) CMOS antenna chip micrograph.  (b) Simulated and measured antenna input SWR
A schematic of the proposed CMOS on-chip antenna is shown in Fig. 1. The antenna consists of a director element, a driven element, a reflector element and a ground plane. Except the reflector element is on the first-metal-layer (M1), all others are on the sixth-metal-layer (M6). As shown in Fig. 2, a transition is used to convert the CPW mode at the input to the CPS mode feeding the driven element. The figure also illustrates the HFSS port excitation of the on-chip antenna.  The radiation boundary condition is applied in the HFSS simulation. One slot line in the CPW is terminated by open circuit and an air-bridge (M1 and via16) connects the two strips of CPW. The air-bridge can keep two ground planes at the same potential [8], [9]. The length of the driven element, the director and reflector elements should be around 0.5λeff, 0.45λeff and 0.6λeff according to the Yagi design principles [10]. Here, λeff is the effective wavelength calculated by assuming the following value for the effective dielectric constant of the substrate; εeff = (εr+1)/2, [11], [12], where εr  is the dielectric constant of the silicon substrate. Table I listed the antenna dimensions.


Fig.4  Simulated antenna radiation power patterns in the XZ-plane and YZ-plane at 60GHz.
Fig.5  Illustration of the on-wafer measurement setup for the power gain of the on-chip antenna.
Fig.3 shows the fabricated CMOS Yagi-antenna chip micrograph and on-wafer measured input VSWR. The chip size is 1.1 x 0.95 mm2.  The input VSWR of the CMOS antenna is less than 2 from 55 to 65 GHz.  Fig. 4 shows the simulated antenna radiation power patterns in the XZ-plane and YZ-plane at 60GHz. The simulated maximum antenna power gain and the front-to-back ratio at 60GHz are about -8 and 9 dB, respectively.  Note that the antenna power gain (absolute gain) Gp is defined as

Gp = directive gain × radiation efficiency.  (1)

The simulated antenna radiation efficiency is about 10 %, which may be due to the CMOS substrate loss. The absolute power gain of the antenna was measured on-wafer with the technique presented in [13]. In the on-wafer antenna power gain measurement, two identical on-chip antennas are placed face-to-face with a distance R, as shown in Fig. 5. One antenna is used as a transmitting antenna and the other as a receiving antenna.  It is noted that the separated distance R between two identical antennas should be satisfied with the far-field condition, which is equal to or greater than [13], where D and λ0 are the largest aperture dimension of the on-chip antenna and the free-space wavelength at the operating frequency, respectively. From the Friis power transmission formula, the maximum antenna power gain (in the central forward direction of the antenna) is given by
where Gt and Gr is the power gain of the transmitting and receiving antenna, Pt is the power transmitted, and Pr is the power received. Similarly, since the two antennas are identical, Gt = Gr = G. The power ratio Pr / Pt is the measured direct transmission coefficient from the vector network analyzer (VNA).  The measured maximum antenna power gain at 60 GHz is about -10.6 dBi. Table I shows the performance summary of the antenna radiation characteristics. Table II lists the performance comparison of the 60-GHz CMOS on-chip antenna with the reported work.


A 60-GHz millimeter-wave on-chip Yagi antenna is presented for 60-GHz WPAN CMOS transceiver application. The CMOS antenna is fabricated with a 0.18-μm standard CMOS process. The antenna chip size is 1.1 × 0.95 mm2. A feeding network is designed in coplanar waveguide technology. Compare with the qusi-Yagi antenna, the 0.18 μm 6-metal-layer CMOS process allows the proposed Yagi antenna to utilize the first metal-layer (M1) to implement a reflector strip. The on-wafer measurement is conducted to measure the input SWR and the maximum antenna power gain of the on-chip antenna. The simulated antenna radiation efficiency is about 10 %, which may be due to the CMOS substrate loss. The simulated antenna pattern performs an end-fire radiation characteristic, and the front-to-back ration is about 9 dB. The measured input VSWR less than 2 from 55 to 65 GHz. The maximum antenna power gain at 60 GHz is about -10.6 dBi. The designed on-chip Yagi antenna is useful for the integrated design of the 60-GHz CMOS single-chip RF transceiver.


The authors would like to thank the Chip Implementation Center (CIC) of National Science Council, Taiwan, ROC, for supporting the TSMC CMOS process.


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