Research Express@NCKU - Articles Digest (Volume 6 Issue 1)

Recently, lateral DMOS (LDMOS) transistors are widely used in medium-voltage smart-power applications because they are easily integrated into the mature standard CMOS process. When the LDMOS device is used in switching applications, the device experiences avalanche breakdown during on-state to off-state transient because of unclamped inductive load. The maximum electric field of the LDMOS device in avalanche occurs at the Si/SiO₂ interface near the drain side. Even if a rugged device survives breakdown initially, repeatedly operating under avalanche may gradually wear out the device because of high electric field near the drain. To evaluate this reliability concern, this work presents the on-resistance (R_on) degradation of LDMOS transistors caused by avalanche breakdown.

Devices investigated in this study are n-type LDMOS transistors fabricated by a 0.35 μm CMOS compatible technology. The cross section of the device, potential contour, impact ionization contour, and electric field distribution biased under avalanche breakdown is shown in Fig. 1. The channel region (Lch) and accumulation region (Lacc) are also indicated in the figure. The device has the following characteristics: the typical operating drain voltage (V_ds) and gate voltage (V_gs) is 12 V, off-state breakdown voltage is 19.3 V, and R_on is 7 mΩ-mm². To evaluate the damage created during fast on-off transient, constant-current pulse stressing is applied to the drain and grounding the source, gate, and p-channel terminals. The stressing is performed at room temperature with various current levels ranging from 1μa to 1 mA. The duration of each pulse is 0.1 s and the number of pulses is 100. During the stressing, R_on is monitored periodically. In addition, charge pumping current (I_CP) is measured to extract stress-induced interface state density (ΔN_it) and oxide trap density (ΔN_ot). The pulse in charge pumping measurement is applied to the gate while the drain and p-channel terminals are grounded. The source terminal is floating because the damage near the source side is negligible. The amplitude of the pulse is fixed at 10 V and the base voltage (V_base) sweeps from -8 V to 0 V under a frequency of 500 kHz. Process (TSUPREM4) and device (Medici) simulations are also performed to investigate the degradation mechanism under avalanche breakdown condition.

Fig. 1. The device cross section and TCAD simulation results on potential contour (line), impact ionization contour (field), and electric field (vector) of our LDMOS device under avalanche breakdown condition.

The relationship between R_on degradation and the number of current pulse under various current levels is shown in Fig. 2 and two observations are found. First, higher current level produces larger R_on degradation at the beginning but eventually R_on degradation saturates at roughly 14%. Second, the magnitude of R_on degradation is closely related to the product of current level and the number of pulses. For instance, the R_on degradation under 10 stressing for 10 pulses is roughly equal to the R_on degradation under 100 stressing for 1 pulse. Such a result reveals that avalanche-breakdown-induced damage is determined by the total charge flowing through the drain. To identify the mechanism of breakdown-induced R_on degradation, charge pumping measurement and TCAD simulation are performed. Fig. 3 shows the I_CP data of the device before and after 10μa current pulse stressing. Based on TCAD simulation results of flat-band voltage and threshold voltage along Si/SiO₂ interface, it can be found that ΔN_it located in the Lch, Lacc, and spacer region can be sensed when V_base = -8 V. At V_base = -4 V, however, only ΔN_it created in the Lch and Lacc region can be probed. According to I_CP data in Fig. 3, little increase of I_CP (ΔI_CP) at V_base = -4 V but significant ΔI_CP at V_base = -8 V indicates that most of the ΔN_it appears under the spacer region. To confirm the location of ΔN_it, lateral distribution of ΔN_it is extracted from ΔI_CP data and the result is depicted in the inset of Fig. 3. It shows that ΔN_it is distributed under the spacer region centered at 70 nm away from the poly-gate edge and the width of distribution is less than 20 nm.

Fig. 3. I_CP data of the device before and after 10μa current stressing for 100 pulses. ΔN_it distribution is shown in the inset. The origin of X-axis in the inset is the poly-gate edge.

Fig. 2. R_on degradation as a function of the number of current pulse under various current levels.

As the number of stress pulse increases, in addition to ΔN_it, a left shift in the I_CP vs. V_base characteristics indicates that positive oxide-trapped charges (ΔN_ot) are also created. The density of oxide-trapped charges can be extracted and the peak value of ΔN_it distribution and ΔN_ot distribution as a function of the number of current pulse is drawn in Fig. 4 and two phenomena are evident. First, ΔN_it is roughly 10 times greater than ΔN_ot, suggesting that the main mechanism responsible for R_on degradation is interface state generation. Second, both ΔN_it and ΔN_ot saturate as the number of current pulse increases. This trend is identical to the saturation of R_on degradation as seen in Fig. 2. The results in Figs. 1 – 4 suggest the mechanisms responsible for breakdown-induced R_on degradation are as follows. Avalanche breakdown results in significant impact ionization near the drain. The electrons generated by impact ionization flow to the drain. Most of the holes created by impact ionization go to p-channel. However, some of the holes can inject into the gate oxide because the direction of the electric field near the drain is from drain toward the gate as in Fig. 1. Such hole injection leads to interface state generation and positive oxide-trapped charges. Although positive ΔN_ot can attract electrons under the spacer and reduce series resistance, ΔN_it is much greater and leading to R_on degradation. Since ΔN_it is distributed in a narrow region, the available interface trap sites are limited, leading to the saturation of ΔN_it. Positive ΔN_ot also has the tendency to saturate as in Fig. 4. The saturation of ΔN_it and ΔN_ot is responsible for the saturation of breakdown-induced R_on degradation.

Fig. 4. The peak value of ΔN_it and ΔN_ot as a function of the number of current pulse.

In conclusion, R_on degradation in LDMOS transistors operated under avalanche breakdown has been discussed. Interface state generation is the main degradation mechanism. TCAD simulation suggests that the driving force of damage is breakdown-induced hole injection near the drain. The degradation of R_on saturates because of the saturation in interface state generation. Since the device experiences avalanche breakdown during unclamped inductive switching, breakdown-induced R_on degradation should be taken into consideration during product design and manufacturing.